发明名称 Phase-locked loop circuit
摘要 A PLL circuit includes a voltage controlled oscillator (VCO), a phase comparator detecting phase difference between a reference signal and a feedback signal provided from the VCO, an input voltage control unit controlling input voltage to be provided to the VCO according to the phase difference detected by the phase comparator, a switching unit switching a value of the input voltage to be provided to the VCO, and a switching timing control unit controlling a switching timing of the switching unit based on the given reference signal, wherein the VCO controls a frequency of the feedback signal according to the input voltage provided from the input voltage control unit. As a result, the VCO can rapidly make the feedback signal in phase with the reference signal and therefore it is possible to effectively reduce the required lock-up time.
申请公布号 US2003214330(A1) 申请公布日期 2003.11.20
申请号 US20030418167 申请日期 2003.04.18
申请人 FUJITSU LIMITED 发明人 TANIGASHIRA SYOUICHI;BABA HIROSHI
分类号 H03L7/093;H03L7/089;H03L7/107;H03L7/18;(IPC1-7):H03L7/06 主分类号 H03L7/093
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