发明名称 Circuit for capturing frame sync signal in receiver
摘要 I and Q symbol streams are demodulated from a received signal of a wave to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal respectively having a 20-symbol length and an 8 PSK-modulated digital signal are time-multiplexed by a demodulating circuit (1). BPSK-demapped bit streams B0 to B3 are generated by a BSPK demapper (3) in accordance with criterion border lines obtained by rotating a basic BPSK criterion border line and a basic criterion border line whose received-signal points are the same as Q-axis on, I-Q phase plane by pi/4, 2pi/4, and 3pi/4 counterclockwise. When a pattern having is a difference of several bits at most from a frame-synchronizing signal is captured from B0 to B3 by first comparing circuits 60 to 63 and thereafter, a pattern having a difference of several bits at most from a superframe-identifying signal is captured by second comparing circuits 64 to 67 after a predetermined certain time, a frame-synchronizing-signal-capturing-signal generating circuit (90) outputs a frame-synchronizing-signal capturing signal (SYN).
申请公布号 US6625239(B1) 申请公布日期 2003.09.23
申请号 US20000581259 申请日期 2000.06.27
申请人 KABUSHIKI KAISHA KENWOOD 发明人 SHIRAISHI KENICHI;HORII AKIHIRO
分类号 H04J3/06;H04L7/04;H04L27/22;(IPC1-7):H04L7/00;H04J11/00;H04L27/06;H04D1/00 主分类号 H04J3/06
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