发明名称 |
System for programming verification |
摘要 |
System for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device. The system operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.
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申请公布号 |
US6621741(B2) |
申请公布日期 |
2003.09.16 |
申请号 |
US20020062283 |
申请日期 |
2002.01.30 |
申请人 |
FUJITSU LIMITED |
发明人 |
YANO MASARU |
分类号 |
G01R31/28;G11C16/02;G11C16/04;G11C16/06;G11C16/34;(IPC1-7):G11C16/04 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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