| 摘要 |
PROBLEM TO BE SOLVED: To improve the total CPU performance, and to reduce the physical size and the power to be consumed by a cache memory. SOLUTION: An L2 cache 502 is controlled by an L2 tag 506 via a bus 510 and by an L3 tag 508 via a bus 512. The L3 cache 504 is controlled only by the L3 tag 508 via the bus 512. The L2 cache 502 is a part of the L3 cache 504, the information 514 stored in the L2 cache 502 is also stored in the L3 cache 504. Since the information 514 stored in the L2 cache 502 is also stored in the L3 cache 504 simultaneously, light-back is generated in both the L2 cache 502 and the L3 cache 504. COPYRIGHT: (C)2003,JPO
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