| 摘要 |
A ferroelectric memory comprises wordlines that cross over bitlines with a ferroelectric cell at each crossing. When reading a select cell of the array, sneak currents are drawn from an active bitline. An integration amplifier begins integrating charge propagated by the active bitline, and an active wordline receives a read level voltage. A first integration value is then obtained from the integration amplifier. Following the first integration, the integration amplifier is cleared and the voltage of the active wordline reduced to a quiescent level. Integration and wordline activation are again performed to obtain a second integration value. The second value is subtracted from the first, and the difference compared to a threshold to determine a data value.
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