发明名称 INPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an input buffer circuit wherein even when variations of a process are increased, variations of threshold voltages determining a high level and a low level are prevented from being increased following the foregoing variations of the process. SOLUTION: In an input buffer circuit, previous stage circuits are adapted to be those having different logical threshold voltages, respectively, and outputs of the foregoing circuits are connected to gates of a P type MOS transistor and an N type MOS transistor connected in series both in later stages. Logical threshold voltage in the later stage lies between the different threshold voltages of both circuits in the previous stage. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003168965(A) 申请公布日期 2003.06.13
申请号 JP20010363826 申请日期 2001.11.29
申请人 OKI ELECTRIC IND CO LTD 发明人 NAGAYAMA ATSUSHI
分类号 H01L27/092;H01L21/8238;H03K19/003;H03K19/0175;(IPC1-7):H03K19/017;H01L21/823 主分类号 H01L27/092
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