发明名称 Method of via formation for multilevel interconnect integrated circuits
摘要 A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.
申请公布号 US6531783(B1) 申请公布日期 2003.03.11
申请号 US19950436133 申请日期 1995.05.08
申请人 STMICROELECTRONICS, INC. 发明人 KALNITSKY ALEXANDER
分类号 H01L21/3213;H01L21/311;H01L21/3205;H01L21/768;(IPC1-7):H01L29/40 主分类号 H01L21/3213
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