| 摘要 |
A capacitor of a semiconductor memory device includes a substrate having a cell pad exposed through a buried contact hole of an interlayer insulating layer; a storage electrode having a bar pattern formed on the interlayer insulating layer for making an electrical connection with the cell pad through the buried contact hole and conductive spacers formed on the side walls of the bar pattern; a dielectric layer formed on the storage electrode; and a plate electrode formed on the storage electrodes with the dielectric layer being between the storage electrode (including the spacers) and the plate electrode. Even if the storage electrode formed in the buried contact hole is partially exposed due to a misalignment between the bar pattern of the storage electrode and the buried contact hole, causing an etched groove to be formed at the periphery of the storage electrode exposed by the over-etching process, the conductive spacer fills in the etched groove to thereby increase the breakdown voltage of the dielectric layer of the storage electrode. In addition, in the following processes for forming the dielectric layer and plate electrode, the bar pattern of the storage electrode does not collapse and the buried contact resistance does not get higher between the bar pattern of the storage electrode and cell pad. Yield of the semiconductor memory device is improved.
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