| 摘要 |
An interface control apparatus for a frame buffer including a byte swapping/sampling controller connected between the PCI host bus and a FIFO (First In First Out) for performing a data conversion between a big Endian data and a little Endian data or a data conversion between a system data and a user data, a byte conversion/view selection controller connected between the FIFO and the SRAM for converting a pixel data stored in the FIFO from a 8 bit-1 byte data to a 9 bit-1 byte data in accordance with a view selected or converting a pixel data stored in the SRAM from a 9 bit-1 byte data into a 8 bit-1 byte in accordance with a view selected, a RAC for controlling a transmission of a pixel data between the SRAM and the RAM but DRAM, and a display controller for receiving a pixel data outputted from the RAM bus DRAM through the RAC and outputting to the RAMDAC through the display bus, for thereby concurrently performing a pixel data conversion between a big Endian and a little Endian and a pixel data conversion for a 8 bit-1 byte and 9 bit-1 byte in a 8 bit-1 byte PCI host bus and a 9 bit-1 byte RAM bus DRAM each using a system memory having different byte definition and bus-endian.
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