| 摘要 |
<p>Soft synchronization effected by slightly changing the period of the generated clock pulse signal (a) can modify this clock pulse signal in such a manner that a phase difference (c) between the stabile clock pulse signal (b), which is generated by a phase locked loop (PLL) (6) on a synchronization signal (S), and the clock pulse signal (a), which is generated for the application (4), slowly decreases until, after a certain period of time, both clock pulse signals (a, b) are synchronous with one another. As a result, the generated clock pulse signals (a) largely retain their period thereby ensuring that, with this clock pulse, cyclically called-up applications can be completely run with the precision required. While variations in the period of the first clock pulse generator, which are regulated by the PLL (6), are reproduced on the second clock pulse generator, a phase difference (c) to be compensated for remains constant. The process of the soft synchronization thus differs only slightly from the normal operating state.</p> |
