SIGNAL TRANSFER CIRCUIT FOR EQUALIZING DIFFERENT DELAY CHARACTERISTICS, METHOD FOR TRANSFERRING SIGNAL, AND DATA LATCH CIRCUIT OF SEMICONDUCTOR DEVICE HAVING THE SAME

摘要

PURPOSE: A signal transfer circuit for equalizing different delay characteristics, a method for transferring a signal, and a data latch circuit of a semiconductor device having the same are provided to equalize each delay time of signal transfer lines having different delay characteristics. CONSTITUTION: The first and the second signal transfer lines(42,44) receives the first and the second input signals(IS1,IS2), delays the received signals(IS1,IS2) during the first delay time and the second delay time, and outputs the delayed signals(TS1,TS2). A slave variable delay stage(45) is connected directly with the second signal transfer line(44) in order to equalize the first delay time and the second delay time. The delay time of the slave variable delay stage(45) is equal to a difference between the first delay time and the second delay time. A reproduction signal transfer line(46) is used for controlling the delay time of the slave variable delay stage(45) and the difference between the first delay time and the second delay time. A master variable delay stage(43) is connected directly with the reproduction signal transfer line(46). The reproduction signal transfer line(46) receives the first input signal(IS1). A controller(48) receives an output signal(OS1) of the first signal transfer line(42) and an output signal(VS) of the master variable stage(43). The controller(48) outputs a control signal(CONT) by comparing phases of inputted signals(OS1,VS).