发明名称 Digital signal processor with coupled multiply-accumulate units
摘要 Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.
申请公布号 AU3984401(A) 申请公布日期 2001.09.03
申请号 AU20010039844 申请日期 2001.02.23
申请人 QUALCOMM INCORPORATED 发明人 GILBERT C SIH;XUFENG CHEN;DE D. HSU
分类号 G06F7/00;G06F7/544;G06F17/10 主分类号 G06F7/00
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