| 摘要 |
PROBLEM TO BE SOLVED: To remove a duty imbalance and a phase error existing in two-phase encoder pulses. SOLUTION: This detector is made up of a frequency quadrupling circuit 1 for generating quadrupled pulses 12 and a code signal 13 from the encoder pulses 14, a counter circuit 2 for counting the pulses 12, a first timer circuit 5 for counting clock pulses from a reference-clock generating circuit 4, a first timer memory means 6 for latching the count of the circuit 5 by each latch signal 18 from others, a second timer memory means 8 for latching data of a second timer circuit 7 reset by each of the pulses 12, an A-phase/B-phase state decoder 9 for receiving the pulses 12 and the signal 13 to generate an A-phase/B-phase edge signal, an A-phase rising edge signal, and an A-phase/B-phase state detecting signal 21, a third timer circuit 22 for counting the clock pulses from the circuit 4 to latch them by the A-phase/B-phase edge signal and to reset them by the A-phase rising edge signal, a correction-value detecting register 10 for recording/holding an output from the circuit 22, a correction- value setting register 11 for recording/holding the signal 21 and a detected correction value 23 from the register 10 as correction values, and an adding/subtracting circuit 18 for adding/subtracting an output of the circuit 2 to/from that of the register 11.
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