| 摘要 |
PURPOSE: A method for forming a multilevel interconnection line of a semiconductor device is provided to reduce contact resistance by increasing contact area with a plug, to prevent an open failure caused by misalignment, and to obviate electrical defects by residual plug material. CONSTITUTION: In the method, a planarized interlayer dielectric layer(104) is formed on a semiconductor substrate(100) having a lower interconnection line(102). Next, a conductive layer(106) is formed on the interlayer dielectric layer(104). The conductive layer(106) and the interlayer dielectric layer(104) are then sequentially etched to form a via hole exposing a portion of the lower interconnection line(102). Next, the plug(110) of conductive material is formed in the via hole, and then the conductive layer(106) is selectively etched to form an upper interconnection line. In addition, a capping metal layer(112) may be optionally formed thereon. Particularly, the upper interconnection line(106) is contacted with a lateral side of the plug(110) instead of topside in a conventional method.
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