| 摘要 |
PROBLEM TO BE SOLVED: To reduce junction capacitance in an FET on a semiconductor substrate. SOLUTION: Implantation depth of N++ ion is formed shallower in a portion of a drain region 3A and a source region 3B in an N-channel junction field effect transsistor(JEFT), and a junction region is reduced between the gate and the drain and between the gate and the source. As a result, the capacitance in the p-n junction is reduced between the gate/drain and between the gate/ source. For the purpose of shallowing depth in a portion of N++ impurity on the gate region 9 side of the drain region 3A and the source region 3B, the thickness of Si3N4 films 2, 5 for reducing damage on ion implantation grows thicker locally, resulting in shallow ion implantation. For example, by forming the Si3N4 layers 3, 4 in two stages, the thickness of the Si3N4 films for protecting damage of ion implantation can grow thicker locally.
|
