发明名称 |
METHOD FOR MANUFACTURING METAL INTERCONNECTION OF SEMICONDUCTOR MEMORY |
摘要 |
PURPOSE: A method for manufacturing a metal interconnection of a semiconductor memory is provided to prevent a characteristic of a metal interconnection from being deteriorated even when an integration degree of the semiconductor memory becomes higher, by forming a barrier metal layer and a plug which have a thickness thicker than a predetermined thickness. CONSTITUTION: An insulating layer(2) is deposited on a substrate in which a semiconductor device is formed. After a contact hole is formed on the insulating layer to expose a specific region of the semiconductor device, a lower metal interconnection material connected to the specific region of the exposed semiconductor device is deposited. A metal pattern for a plug is formed on a part of an upper portion of the lower metal interconnection material. A barrier metal layer(6) is formed on the metal pattern for the plug and the lower metal interconnection material. The barrier metal layer and the lower metal interconnection material are patterned to form a lower metal interconnection(3). After an insulating layer is deposited and planarized on the entire structure, an interlayer dielectric(5) is formed by exposing the barrier metal layer deposited on the metal pattern for the plug. A metal layer is deposited and patterned on the entire structure to form an upper metal interconnection(8) connected to the exposed barrier metal layer.
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申请公布号 |
KR20010027699(A) |
申请公布日期 |
2001.04.06 |
申请号 |
KR19990039580 |
申请日期 |
1999.09.15 |
申请人 |
HYUNDAI MICRO ELECTRONICS CO., LTD. |
发明人 |
LIM, SEONG HYEOK |
分类号 |
H01L21/77;(IPC1-7):H01L21/77 |
主分类号 |
H01L21/77 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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