| 摘要 |
The memory comprises a number of memory banks (00...15,) each having a memory/storage cell array, in which a number of storage cells are arranged in the matrix. Also included is an address decoder for selecting a cell of the matrix of cells. A device (61-65) is provided for supplying an address comprising a number of address bits (ADR), through which one cell of the memory cells can be selected by driving the address decoder. A first memory bank decoder (110) has a first part of the address bits and a first release/enable signal (EN1) supplied to it on the input side, and through the output side a bank selection signal is generated for each memory bank of the first group (00....07), so that one of the memory banks of the first group can be selected. A second memory bank decoder (120), identical to the first (110), has the first part of the address bits and a second release/enable signal (EN2) supplied to it on the input side. Through the output side a bank selection signal can be generated for each memory bank (08...15) of the second group, so that one of the memory banks of the second group can be selected. A pre- decoder (51), which contains a logic circuit (511-514) on the input side, has a second part of the address bits as well as a further release/enable signal supplied to it, and through the output, the first and second release/enable signals can be generated as complementary signals.
|
