发明名称 TIMING CONTROL CIRCUIT DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To quickly execute phase synchronization, to adjust a phase difference without depending on an output load based on clock signal distribution or the like and to attain low skew and low power consumption in a timing control circuit for synchronizing a phase difference between an input clock signal and an output clock signal. SOLUTION: The timing control circuit device is constituted of a rough timing control circuit CDLL11 for roughly adjusting a phase difference between an input clock signal and an output clock signal, a fine timing control circuit FDLL11 for finely adjusting the phase difference and a rough/fine conversion circuit CONV11 for transmitting a clock signal from the circuit CDLL11 to the circuit FDLL11. The circuit FDLL11 highly accurately adjusts the phase difference between an input clock signal clkin11 and an output clock signal clkout11 by using a roughly adjusted signal to remove the phase difference.</p>
申请公布号 JP2000298532(A) 申请公布日期 2000.10.24
申请号 JP19990107542 申请日期 1999.04.15
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 MIYAZAKI SUKEYUKI;HASEGAWA KIYOSHI;KOKUBO MASARU;AOKI HIROKAZU;ISHIBASHI KOICHIRO
分类号 G06F1/10;G11C11/407;G11C11/4076;H03K5/13;(IPC1-7):G06F1/10 主分类号 G06F1/10
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