发明名称 INTERRUPTION PROCESSOR
摘要 PROBLEM TO BE SOLVED: To arrange a program area in arbitrary actual addresses and to effectively use the storage device by accepting an interruption initiated during the execution of a program allocated to arbitrary addresses (actual address) on a main storage and executing the interruption processing routine corresponding to the kind of the initiated interruption. SOLUTION: When the interruption is initiated, a computer system stores the contents of a PSW 102 in corresponding old PSWs 105 to 110 for interruption, stores the contents of an EXR register 103 in corresponding old EXRs 117 to 122 for interruption, and writes the contents of corresponding new PSWs 111 to 116 for interruption to the PSW 102 and clear the EXR register 103 to 0. Consequently, even when the program being executed at the time of the initiation of the interruption and an interruption processing routine are arranged in different actual storage sections, the process can normally be carried on. Thus, the interruption processing in the allocated program execution is enabled.
申请公布号 JP2000215067(A) 申请公布日期 2000.08.04
申请号 JP19990016627 申请日期 1999.01.26
申请人 HITACHI LTD 发明人 KIYOI MASAHIRO;NAGASUGA HIROFUMI;OCHI FUTOSHI
分类号 G06F12/02;G06F9/46;G06F9/48;G06F12/06;(IPC1-7):G06F9/46 主分类号 G06F12/02
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