发明名称 |
Control circuit for column address strobe delay in SDRAM has control circuit unit for generating four control signals for controlling latches and data selector |
摘要 |
The control circuit has a control circuit unit for generating four control signals for controlling latches and data selector The circuit has a control circuit unit (21) for receiving a clock signal (QCLK) and supplying data and four control signals. A latch (22) supplies or stores internal data based on the first control signal (con3). A second latch operates based on the second control signal. A data selector (25) directly routes the internal data or the data from the second latch based on the fourth control signal. A third latch (24) supplies data from the selector to a data output buffer or feeds the data from the selector based on the third control signal. An Independent claim is included for a control circuit.
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申请公布号 |
DE19954564(A1) |
申请公布日期 |
2000.05.18 |
申请号 |
DE19991054564 |
申请日期 |
1999.11.12 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
KIM, DONG KYEUN;KIM, SUNG HOON |
分类号 |
G11C11/407;G11C7/00;G11C7/10;(IPC1-7):G11C8/18 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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