| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a multiplexer with simpler configuration at lower cost with less number of components as compared with a conventional multiplexer, where a multiplexed signal is outputted synchronously with an external clock and an internal clock and a central processing unit in a control means executes time information on management, without provision of hardware exclusively used for the external clock and the internal clock and without a dummy packet generating circuit. SOLUTION: A buffer 251 receives a data transfer block and a packet multiplexed signal from a multiplexer section and writes the multiplexed signal synchronously with the data transfer clock, and reads out the stored multiplexed signal synchronously with an internal clock or an external clock selected by a clock changeover switch 252. A packet counter 253 receives a reference signal from a multiplex control section 26, counts the output transfer data of the buffer 251 and outputs a count of a packet number per reference time to a CPU in the multiplex control section 26. The CPU sets a data transfer clock frequency of the multiplexer section and controls the multiplexer section, based on the comparison result between the count and a theoretical value.</p> |
