发明名称 Voltage monitoring circuit capable of reducing power dissipation
摘要 In a buffering circuit, a CMOS inverter is connected between a node and a ground terminal. A source-follower-type MOS transistor is connected between a power supply terminal and the node, and a approximately definite voltage is applied to a gate of the source-follower-type MOS transistor. A MOS transistor is connected in parallel to the source-follower-type MOS transistor, and an inverted signal of an output signal of the CMOS inverter is applied to a gate of the MOS transistor.
申请公布号 US5929679(A) 申请公布日期 1999.07.27
申请号 US19970823001 申请日期 1997.03.21
申请人 NEC CORPORATION 发明人 OHWADA, MASAKATSU
分类号 G01R19/165;H03K5/08;H03K5/24;H03K19/00;H03K19/003;H03K19/0948;(IPC1-7):H03K3/037;H03K5/22 主分类号 G01R19/165
代理机构 代理人
主权项
地址
您可能感兴趣的专利