| 摘要 |
A floating point arithmetic unit is provided which effectuates arithmetic operations upon floating point numbers. A comparator unit, which may be implemented using a carry-skip chain, determines the relative magnitudes of the exponents of the floating point numbers to be operated upon. A first ripple carry subtractor unit formed within a first ripple carry shifter subtracts a first value corresponding to the exponent of a first of the floating point numbers from a second value corresponding to the exponent of a second of the floating point numbers. A second ripple carry subtractor unit formed within a second ripple carry shifter subtracts the second value from the first value. When certain lower order bit results of the exponent value subtraction operations of each ripple carry subtractor are obtained, the mantissa of the floating point number with the smaller exponent provided to one of the carry ripple shifters is shifted to the right by a number of positions dependent upon the lower order bit results. Effectuation of this shift operation begins before determining certain intermediate order and high order bit results of the subtraction operation. When certain intermediate bit results of the exponent subtraction operation are obtained, further shifting of the mantissa is effectuated before the highest order bit results of the subtraction operation are determined. A final shift operation is effectuated upon determining the highest order bit results of the ripple carry subtraction operation. An output signal from the comparator unit, which determines the relative magnitudes of the exponents of the two floating point numbers being operated upon, selects the shifted mantissa output from the ripple carry shifter associated with the mantissa of the floating point number with the smaller exponent. This shifted mantissa is provided to an input of an adder/subtractor unit.
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