| 摘要 |
PROBLEM TO BE SOLVED: To surely read out data from a cell at high speed and to arrange easily a metal wire connected to a bit line terminal and a ground line terminal when integration density of a circuit is increased. SOLUTION: Bit line spreading wirings 1 of total four lines are connected individually to each drain of a cell of each column (four columns) from two bit line terminals D0, D1, also, four bit line spreading wirings from one virtual ground line terminal out of virtual ground line terminals VG1-VG3 are connected individually to each source of a cell of the four columns. Also, bank selection transistors BT1-BT6 are arranged for each bit line spreading wirings 1, 2 respectively. |
