发明名称 Digital controlled oscillation circuit and PLL circuit
摘要 <p>A digital controlled oscillation circuit comprises a first delay circuit (11) for delaying a first signal (S1) by a control signal (S13) and outputting the same as a first delay signal (S2); a second delay circuit (12) for delaying a second signal (R1) by a control signal (S14) and outputting the same as a second delay signal (R2); an RS flip-flop (20) which switches a first output signal (out) from low to high and switches a second output signal (/out) from high to low and outputs the same when receiving as its input the first delay signal (S2), while switches the first output signal (out) from high to low and switches the second output signal (/out) from low to high and outputs the same when receiving as its input the second delay signal (R2); and first and second switching detection circuits (15, 16) for generating first and second signals (S1, R1) and outputting the same to the first and second delay circuits (11, 12) when detecting that the first and second output signals (out, /out) switch from high to low. <IMAGE></p>
申请公布号 EP0901226(A2) 申请公布日期 1999.03.10
申请号 EP19980402180 申请日期 1998.09.03
申请人 SONY CORPORATION 发明人 YANAGIUCHI, HIROSHI
分类号 G11C11/4076;H03K3/03;H03K5/13;H03K5/131;H03L7/099;(IPC1-7):H03K3/03 主分类号 G11C11/4076
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