| 摘要 |
PROBLEM TO BE SOLVED: To improve a PLO characteristic and to reproduce a clock that has a good quality by making a reference clock that is inputted to a PLO circuit of a clock reproducing means into an N dividing clock. SOLUTION: An N dividing RTS generating circuit 1-6 calculates an RTS series for N dividing and outputs it, and a comparator circuit 1-7 compares a dividing RTS value from the circuit 1-6 with a count value from a 4-bit counter 1-8 and outputs a pulse when they coincide with each other. When an Mmm counter 1-9 receives a main part Mmm for N dividing from an N dividing RTS differential series counting circuit 1-3 and counts a network clock Mmm times, it outputs an 'ON' signal. A gate circuit 1-10 outputs a pulse signal from the circuit 1-7 only when a signal from the counter 1-9 is ON. A pulse signal from the circuit 1-10 is outputted whenever a network clock Mmm count + N dividing RTS value is counted. A signal that is inputted to a PLO circuit 1-11 is made into an N dividing clock for a CBR signal clock. |
