| 摘要 |
PROBLEM TO BE SOLVED: To make the layout design of a dynamic RAM, etc., which uses a stand-by current reduction method efficient and reduce the man-hours for the design. SOLUTION: Metal wiring layers which are to be the power supply voltage supply nodes or ground potential supply nodes of CMOS logic gates of an inverter, etc., in a dynamic RAM, etc., are arranged so as to cross a main power supply voltage supply line MVCS, a sub-power supply voltage supply line SVCS, a main ground potential supply line MVSS and a sub-ground potential supply line SVSS. Contacts CON11-CON41 and CON12-CON42 are selectively formed by a master slice to make the interconnections to any power supply voltage supply line and any ground potential supply line easy. With this constitution, various types of CMOS logic gates having different connection patterns required for a stand-by current reduction can be obtained by common cell patterns. |
