| 摘要 |
A third-order sigma-delta analogue-to-digital conversion circuit has three individual LC filter circuits 11,12,13, a quantization circuit 20 and a monitoring circuit 30. The monitoring circuit 30 detects a predetermined, periodic pattern in the output bit stream. The periodicity of this pattern is when f c is the converter sampling frequency and f r is the resonant frequency of the filter. If the pattern is detected indicating oscillation of the conversion circuit, the monitoring circuit 30 resets the filter.
|
