| 摘要 |
An effective signal detection circuit for serial transmission apparatuses using bi-phase code is provided, which effective signal detection circuit facilitates reducing variation of characteristics, current consumption, and dimensions thereof. The effective signal detection circuit comprises a shift register further comprising three D-FFs connected in a series input and parallel output circuit; and a determining circuit further comprising an AND element, an NOR element, and a NOR element. A clock pulse having a frequency twice as high as the bit frequency of a bi-phase coded input signal RX is fed to the clock terminals of the D-FFs. The shift register obtains, based on the clock pulse, a parallel signal bundle Q1, Q2, Q3 corresponding to three consecutive half bits of the input signal RX. The parallel signals Q1, Q2, Q3 are input to the input terminals of the AND element and the NOR element connected in parallel. The output terminals of the AND element and the NOR element are connected to the input terminals of the NOR element. The NOR element 33 outputs a DV signal indicating existence or non-existence of an effective input signal RX.
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