发明名称 MANUFACTURE OF TRANSISTOR ARRAY
摘要 <p>PROBLEM TO BE SOLVED: To reduce the number of photolithographic treatments. SOLUTION: An ITO film 22 and a chromium film 23 are formed, a drain line 24, which is two-layer structure of the ITO film 22 and the chromium film 23, a drain electrode 26 and a source electrode 26 are formed by the first photolithographic treatment, and a picture element electrode 28 is formed by the ITO film 22 by conducting the second photolithographic treatment. Then, a semiconductor layer 31, a gate insulating film 32 and an aluminum film 34 are formed. In this case, phosphorus diffusion layers 30 are formed on the prescribed position. Then, a gate line 35 is formed by the aluminum film 34 by conducting the third photolithographic treatment, and at the same time, the gate insulating film 32, the aluminum layer 31 and the diffusion layer 30 are left only on the part under the gate line 35. As the chromium film 23 on the end part of the drain line 24 is exposed under the above-mentioned state, a driver IC chip can be bonded to the exposed part.</p>
申请公布号 JPH09186334(A) 申请公布日期 1997.07.15
申请号 JP19950351231 申请日期 1995.12.27
申请人 CASIO COMPUT CO LTD 发明人 SHIMOMAKI SHINICHI
分类号 G02F1/136;G02F1/1368;H01L21/336;H01L29/786;(IPC1-7):H01L29/786 主分类号 G02F1/136
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