Semiconductor memory device flash EEPROM, SRAM memory - has read circuit with selection transistor electrode terminal directly coupled to memory bit line and control terminal supplied with constant selection voltage

摘要

The memory device includes a number of memory cells and a read circuit (11). The memory cells are formed at the intersection points of a matrix of bit lines and word lines. The read circuit reads data signals corresponding to the data content of the memory cells. Provided with the read circuit are a current amplifier, a selection transistor (N2), and a reference transistor (N1). The selection transistor is associated with one of the bit lines (BL) and has a control terminal (12) together with two electrode terminals (13,14). The bit line is directly coupled to one electrode terminal (13), the control terminal being supplied with a constant selection voltage (SELECT). The control gate (18) of the reference transistor is supplied with a reference voltage (VBIAS). A supply potential (Vdd) or ground is supplied to one reference transistor terminal (15).