| 摘要 |
PURPOSE: To dissolve the increase of a circuit scale by a 90 deg. phase delay device and to accelerate a basic operation speed. CONSTITUTION: A frequency and a phase are compared by an offset compensation digital type phase comparator 3 for inputting clock signals and data signals and the offset ofΔV is applied to its own voltage-phase characteristics corresponding to the voltage phase of a multiplication type phase comparator 4. Further, a voltage level comparator 5 for inputting the output 8 of the offset compensation digital type phase comparator and the output 9 of the multiplication type phase comparator outputs control signals 10 for switching the output 8 of the offset compensation digital type phase comparator and the output 9 of the multipl,ication type phase comparator. Also, the control signals 10 are sent to an output switching device 6 and the output 8 or 9 of the phase comparator is switched and outputted corresponding to the frequency difference and phase difference of the clock signals CLK and the data signals DATA.
|
