| 摘要 |
FIELD: computer engineering. SUBSTANCE: device has n single-bit adding units, n pulse generators (n is bit-length of operands), NOR gate. Each single-bit adding unit has single-bit binary adder, modulo-to adder with inverting input, two AND gates and OR gate. Device implements adaptive disintegration of integral process of addition into several separated processes with its own starting points depending on operands. Sequential calculation of bits of sum in each process of addition is compensated by parallel operations of all processes. EFFECT: increased speed. 1 dwg |
