| 摘要 |
<p>PURPOSE:To perform processing at high speed by providing a control circuit supplying control voltage and a control signal for each latch means, performing simultaneous batch write-in for each memory cell, and performing simultaneous batch read-out from the memory cell. CONSTITUTION:Corresponding latch circuits A1, A2, A3 are connected to each bit line BL1, BL2, BL3 respectively through gate transistors TA1, TA2, TA3, a control signal NA is supplied to gates of these transistors from a control circuit 4. The circuit 4 controls so that control voltage NB is made write-in drain voltage at the time of write-in and it is made read-out drain voltage at the time of read-out. That is, in erasing, electrons are injected in floating gates of all memory cells MC connected to the selected word lines using a tunnel effect by applying high positive voltage to the selected word line. In writing, a drain is extracted from the floating gate of a selected cell by applying negative voltage to a selected word line and applying intermediate voltage to a bit line.</p> |
