Variable width current mirror DAC for IC testing in computer test system

摘要

The method of calibrating a controlled delay device (101) for setting the delay for the positive and negative flanks of an input signal (102,203) depending on control data that includes at least one first data value for a fine adjustment and a second value for a rough adjustment. First, a time reference (932) is set at the desired frequency and then a first element is set to a minimum delay by a control signal (PCN TRL). Then, the input signal (203) to passed to the device and the phase of the output signal (102,204) is compared with the phase of a system beat (942) by a phase detector (44). The steps described are repeated until this detector gives a value smaller than the system beat a certain no. of times. The delay can be re-set if required.