发明名称 VARIABLE-LENGTH DECODER
摘要 PURPOSE: To attain operation speed included in output data speed by allowing a pointer generation means to read out localizer information directly from an access mechanism means. CONSTITUTION: A large part, especially blocks 50, 52, 54, 56, 60, of an architecture array is driven by K-bit route width. The value of K is determined by the maximum length of a decoded data segment. A stand-by processor 44 for receiving an encoded segment and repeatedly driving a succeeding state through a retro-coupler 45 calculates the length of each encoded segment and stores the calculated length in an FIFO 50 together with the encoded segment. The processor 44 has a fixed input speed and variable output speed. A don't-care-bit position indicating selection to be executed in the case of merging a large new code word into a small new code word is used for the reduction of the size of an FIFO buffer.
申请公布号 JPH0779165(A) 申请公布日期 1995.03.20
申请号 JP19940128859 申请日期 1994.06.10
申请人 PHILIPS ELECTRON NV 发明人 AREKISANDAA MIKAERU RENSHINKU;ARUBERUTO FUAN DERU UERUFU;ROBERUTO ARUBERUTASU BURONDEIKU;UIRUHERUMUSU HENDORIKUSU ARUFUONSASU BURIYUURUSU
分类号 H03M7/40;H03M7/42;H04N1/41;H04N7/24;H04N19/00;(IPC1-7):H03M7/40 主分类号 H03M7/40
代理机构 代理人
主权项
地址