发明名称 NOISE COMPENSATION CIRCUIT
摘要 PURPOSE:To improve noise margin by using a 1st transistor(TR) so as not to increase a level of a node on a next stage more than a specific value when pulse noise is superimposed on a wire and using a 2nd MOS TR to extract a charge of the node by the ground level. CONSTITUTION:Suppose that the height of a pulse noise DELTAV is superimposed on a node N11 via parasitic capacitors Cpa, Cpb by a power supply noise, then a level of a node N12 on a next stage is increased transiently by a MOS TR Tr1 but does not increase to DELTA-Vt or more, where Vt is a threshold voltage of a 1st MOS TR Tr1. Then a charge of the node N12 is extracted by the ground level Vss by a 2nd MOS TR 2. When the DELTAV-Vt is a threshold voltage of the inverter INVc or less, the effect of the noise is not entirely appeared on the node N13. Furthermore, the operation is unchange even when pulse time of a noise is long. Thus, the noise margin is improved.
申请公布号 JPH06334494(A) 申请公布日期 1994.12.02
申请号 JP19930124305 申请日期 1993.05.26
申请人 SANYO ELECTRIC CO LTD 发明人 KABASAWA TAKASHI
分类号 H03K5/1252;H03K5/01 主分类号 H03K5/1252
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