| 摘要 |
PURPOSE: To obtain linearity in the progress of a delay as a function of a control signal. CONSTITUTION: A variably controllable delay circuit is constituted of an signal input section 1, a control input section 3 for controlling signals, a signal output section 2 for sending signals delayed in time with respect to input signals SE, a delaying means incorporating a logic circuit 4 connected between the input section 1 and output section 2, and a load circuit incorporating a capacitive load 10 connected to the output section 9 of the logic circuit 4. The impedance of the load circuit can be changed by the action of a control signal for changing the delay. The capacitive load 10 is made variable by the actions of control signals b3, b2, and b1, having different capacitance values. |
