| 摘要 |
PURPOSE:To simplify the circuit constitution for reproducing of a secondary clock signal to reduce the device scale and the cost. CONSTITUTION:A clock signal S12 from an input terminal 22 is divided by a frequency divider 26 into n/n+1 to generate a clock signal of data. This clock signal is inputted to a speed conversion bit separating circuit 24 and is subjected to bit separation. Data S 14 after separation which has additional bits removed by the speed conversion bit separating circuit 24 and a clock signal S16 after speed conversion are outputted from output terminals 30 and 32 respectively. |
