ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR INTEGRATED CIRCUITS

摘要

A circuit for protecting integrated circuits from electrostatic discharge by using SCR latchup to divert the ESD current pulse away from sensitive circuit structures. The SCR structure of the invention includes a trigger circuit having an NMOS triggering transistor for activating the SCR when an ESD event occurs on an input/output pad of the integrated circuit being protected. The ESD event on the input/output pad of the integrated circuit is detected by a circuit which applies a trigger voltage to the NMOS triggering transistor to initiate latchup of the SCR independent of junction breakdown of the NMOS triggering transistor. The trigger voltage is generated by an inverter trigger or a capacitor trigger powered by the ESD event so as to trigger SCR latchup so long as the integrated circuit is not powered up (VDD is low). The SCR of the invention may also have a floating well whereby the well resistor Rw of the SCR is replaced by a CMOS device which inhibits forward biasing of the pnp base of the SCR when VDD is high but allows small currents to forward bias the pnp base when VDD is low. The NMOS trigger FET of the invention also may be isolated from the substrate containing the SCR so as to further decrease the effects of junction breakdown conditions on the latchup of the SCR.