发明名称 POWER FAILURE COMPENSATING CIRCUIT
摘要 <p>PURPOSE:To improve reliability by detecting the existence of abnormality at a peripheral circuit by measuring energy consumption in a reset state and comparing it with energy consumption in a normal case. CONSTITUTION:The AC power source of AC 100 volts is turned to power failure, power is supplied from a battery 11 to a frequency divider circuit 4, CPU 5, display circuit 6 and oscillation circuit 7 although there is no power supply to a W/F circuit 3. When the power failure is detected, the CPU 5 stores electric energy calculated just before the power failure and transmits a reset signal to the frequency divider circuit 4 and afterwards, the oscillating operation of the oscillation circuit 7 is stopped. The display circuit 6 continuously displays the electric energy stored in the CPU 5. At such a time, a flip-flop is turned to an initial state in the frequency divider circuit 4 by the reset signal and turned to a fixed output state regardless of the number of pulses before that. Therefore, when the energy consumption of the frequency divider circuit 4 in this initial state is set at an abnormal level larger than the normal energy consumption, the existence of a defect is judged.</p>
申请公布号 JPH0540550(A) 申请公布日期 1993.02.19
申请号 JP19910194071 申请日期 1991.08.02
申请人 MITSUBISHI ELECTRIC CORP;TOKYO ELECTRIC POWER CO INC:THE 发明人 NAKADA SEIICHI;YOSHINAGA TORU
分类号 G06F1/32;G06F1/24 主分类号 G06F1/32
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