| 摘要 |
<p>In an interruption circuit for use with a central processing unit (11), each of a multiplicity of interruption generating units (12) can generate an interruption signal upon occurrence of an interruption request. A scanning arrangement (16, 17, 27) scans the units to specify one of them at a time as a particular unit and to supply the signal generated by the particular unit to the CPU (11) as a particular signal. A response supply arrangement (39, 42, 27) supplies the particular unit with a response produced by the CPU upon receipt of the particular signal. Supplied with the response, the particular unit supplies the CPU via a data bus (25) with an interruption vector which is specific to each unit and makes the CPU interrupt its operation related to the particular unit. Preferably, the scanning arrangement comprises a scanning circuit (16) and a first plurality of polling circuits (17), each for a second plurality of generating units with a response control circuit (27) corresponding thereto. <IMAGE></p> |
