| 摘要 |
<p>In a present control circuit for controlling an operation mode in a pseudo-static RAM, a chip enable control circuit (11) generates a first control signal group ( phi CE, phi P1, phi P2) in synchronism with a change in level of a chip enable signal (CE). A second control circuit (12) receives a chip select signal (CS) and first control signal group ( phi CE, phi P1, phi P2), latches a chip select signal (CS) on the basis of the control signal group and generates a second control signal ( phi CS) in accordance with the latched signal. A third control circuit (13) controls a write enable signal (WE) with an inverted replica of the second control signal and inverted replica of a predetermined one of the first control signals in the first control signal group. <IMAGE></p> |
