| 摘要 |
<p>PURPOSE:To prevent erroneous erasure and write on an EEPROM (Electrically Erasable and Programable ROM) performed even when the runaway or malfunction of a CPU occurs by containing a write control terminal and a write control circuit. CONSTITUTION:The write control circuit 4 controls the permission and prohibition of a write operation on the EEPROM 3 corresponding to a level inputted to the write control terminal 6. When the input level of the write control terminal 6 is set at a GND level with a changeover switch 8, no write operation is performed with the write control circuit 4 even when a write signal from the CPU is activated, and no data write on the EEPROM 3 is performed. Therefore, by setting the input level of the write control terminal 6 at the GND level, no data write on the EEPROM 3 is performed even when the runaway or malfunction of the CPU occurs due to an unknown reason. Thereby, the content of the EEPROM 3 can be held semipermanentally.</p> |
