DATA PROCESSING SYSTEM

摘要

The system uses both 15-bit and 31-bit logical addresses. Instructions are 16-bit; some require the 15-bit addresses and some require the 31-bit. The choice is specified by certain combinations of instruction bits 0, 5 and 10 to 15. Blocks of macro-instructions are pre-fetched into instruction cache logic (120). Macro-instruction decode logic (121) decodes the macro-instructions and produces address descriptor bits which specify the required address size. Displacement logic (122) responds to the descriptor bits to convert 15-bit logical addresses to 31-bit addresses. The 31-bit addresses, whether of this size ab initio or produced by conversion from 15-bit addresses are converted into physical addresses by an address translation unit.