发明名称 SEMICONDUCTOR MEMORY DEVICE WITH DEFECT RELIEVE CIRCUIT
摘要 PURPOSE:To enlarge the improving effect of yield in a small area by setting the number (m) of word lines or bit lines, which are simultaneously replaced by defect relief, to the divisor of M smaller than the M when a memory array is divided into the M (M>=2) number of memory mats. CONSTITUTION:For example, when a word line W[i, 0] of a memory mat 110 is selected, a word line W[i, 2] corresponding to a memory mat 112 is simultaneously selected. When the word lines of memory mats 111 and 113 are selected, the word lines of the memory mats 110 and 112 are not selected. For example, when a word line W[0, 0] of the memory part 110 is defective, W[0, 0] and W[0, 2] are simultaneously replaced with an auxiliary word line. However, the word lines of the memory mats 111 and 113 are not replaced. Thus, the number of the memory cells to be simultaneously replaced by the defect relief is reduced. Then, the probability of the defect in the auxiliary line itself is reduced, the improving effect of the yield is made large even in a highly integrated memory.
申请公布号 JPH02192100(A) 申请公布日期 1990.07.27
申请号 JP19890260021 申请日期 1989.10.06
申请人 HITACHI LTD 发明人 HORIGUCHI SHINJI;ETO JUN;AOKI MASAKAZU;ITO KIYOO
分类号 G11C29/00;G11C11/34;G11C11/401;G11C11/413;G11C29/04 主分类号 G11C29/00
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