| 摘要 |
PURPOSE:To attain the single body test of an internal RAM and to automatically generate the test pattern of an internal logical circuit by providing selectors on the input side and output side of the internal RAM. CONSTITUTION:A data input signal DI, an address signal A, a block selection signal Bs, a write enable signal WE, a data input signal for test TDI, an address signal for test TA, a block selection signal for test BS and a write enable signal for test TW are respectively given. First selection circuits (selectors 9-12) selecting plural signals by test signals TM0 and TM1, an intra-RAM circuit 8 to which the selected output signals are inputted, second selection circuits (selectors 13 and 14) selecting the output signals and the output signals of the first selection circuits by the test signals TM0 and TM1 are provided in the internal RAM 7. Thus, the first and second selection circuits are controlled by the combination of the test signals, and the RAM single body test and the automatic generation of the test pattern in the internal logical circuit are attained. |
