| 摘要 |
<p>PURPOSE:To suppress the gate length of a gate electrode to a designed gate length by forming a spacer layer on an operational layer, exposing, reversal- baking and developing positive resist layers for reversing an image on the spacer layer, and etching the spacer layer by means of using the exposed resist layer as a mask. CONSTITUTION:The spacer layer 3 is formed on the surface of a semiconductor substrate 1 possessing the operational layer 2 thereon, and positive resists 4 and 5 for reversing an image are applied to the spacer layer 3, and exposed according to a desired pattern. Then, the positive resists 4 and 5 for reversing an image are reversal-baked, and the entire surface of the positive resist for reversing an image is exposed to develop and remove the positive resist 7 for reversing an image. On the other hand, the positive resist 8 for reversing an image is masked to remove the spacer layer 10. Thus, the gate length of the gate electrode is suppressed to the designed gate length, and moreover, the horizontal spread of recessed width can be suppressed.</p> |
