| 摘要 |
<p>PURPOSE:To prevent erroneous selection of clock signals by latching two clock signals out of four clock signals, which have 50% duty ratio and have phases successively shifted from one another by 1/4 period, in flip flops(FF) and selecting one pertinent clock signal. CONSTITUTION:Four clock signals CLK1-CLK4 have the same period and have phases successively shifted from one another by 1/4 period and have about 50% duty ratio. FFs 1 and 2 latch clock signals CLK1 and CLK2, which are inputted at the rise point of an input signal DIn at the time of input of the signal DIn, and send latched data 11 and 12 to selectors 3 and 9. An FF 4 latches these data by the rise of a clock signal 13 inputted to a clock terminal C and outputs data 14. Thus, data synchronized with the clock of the receiver side is outputted from the FF in the last stage which phase the input signal is inputted with.</p> |
