| 摘要 |
Because of physical and electrical limitations, buffering of the clock in a data processing system often has to be provided by two different Integrated Circuit buffers. If the clock is connected in parallel to all buffer inputs (assuming that was within the clock drive capability) the outputs of one of the Integrated Circuits may be skewed or shifted in delay time relative to the outputs of the other integrated circuit, because of the differences in the buffers. Since, however, the delay times of all the buffers on each chip are nearly the same (to within a guaranteed tolerance typically) the circuit provided by this invention will give outputs all having small and predictable skews.
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